Single-slope ADCs are particularly attractive for use in applications such as column-parallel digitization in image sensors because of their relative simplicity and the fact that key pieces of the circuitry can be shared by all the columns. Additionally, they offer excellent Differential Non-Linearity (“DNL”) and, with careful design of the ramp generator, which is shared, good Integral Non-Linearity (“INL”) as well. Another advantage is that because the ramp is shared, gain matching between the columns is automatic. Their relatively slow speed is mitigated by the large multiplicity of converters.
In many applications, a commonly used circuit comprises a ramp generator and a counter, which generates a code value that tracks the progress of the ramp. Each unit cell contains a comparator and a set of latches that capture the code value at the time the ramp crosses the input voltage, as indicated by the comparator. If continuous-time comparators are used the count must be represented by Gray code to avoid the possibility of error in the capture at code transitions. Gray code is a binary code invented by Frank Gray (see U.S. Pat. No. 2,632,058, issued Mar. 17, 1953) which has the property that only one binary digit (“bit”) switches between successive integer values represented by the code, even when Gray code “rolls over” (e.g., reaches the limit of the values representable by the number of bits used, and goes back to zero, represented by bits, all of which are set to zero). These properties are not present in standard binary code.
Because of the large multiplicity of unit cells, it is important to keep their size and power consumption low. The common approach is to use a transparent latch or flip-flop clocked by the comparator output. However, in both these circuits the internal nodes switch every time the code changes until the comparator trips and freezes the value. This switching produces shoot-through and charging currents. A typical latch in a 3.3 V, 0.35 μm process may consume 0.3 pC each time the input changes in the transparent state. For a code rate of ˜10 MHz, the resulting average current may be comparable to the comparator current. The instantaneous current, multiplied by the number of columns, can be quite large and it will contain very high frequency components which can create noise. As successive comparators trip, freezing the latches, the total current will decrease. This changing power supply loading may lead to crosstalk or linearity issues.
There is a need for an improved latch that can minimize the power consumption and noise generation of the latch or memory of an ADC.